SI4539DY Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – Dual N & P-Channel Enhancement Mode Field Effect Transistor

January 2001
Si4539DY
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
N-Channel 7.0 A,30 V, R_DS(ON)=0.028 Ω @ V_GS=10 V
R_DS(ON)=0.040 Ω @ V_GS= 4.5 V.
P-Channel -5.0 A,-30 V,R_DS(ON)=0.052 Ω @ V_GS=-10 V
R_DS(ON)=0.080Ω @ V_GS=-4.5 V.
High density cell design for extremely low R_DS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
SO-8
SOT-223
SOIC-16
D2
D2
D1
D1
4539
SO-8
G2
S2
pin 1
G1
S1
5
4
6
3
7
2
8
1
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Power Dissipation for Dual Operation
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
R_θJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case (Note 1)
N-Channel
30
20
7
20
2
1.6
1
0.9
-55 to 150
P-Channel
-30
-20
-5
-20
78
40
Units
V
V
A
W
°C
°C/W
°C/W
© 2001 Fairchild Semiconductor International
Si4539DY Rev. A