ES29LV160E Datasheet, PDF (49/53 Pages) Excel Semiconductor Inc. – 16Mbit(2M x 8/1M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory

PHYSICAL DIMENSIONS
48-Ball FBGA (6 x 8 mm)
D
EE SS II
Excel Semiconductor inc.
0.20 _(4x)
A
e
E
D1
H GF E
6
5
4
3
2
1
DCB A
7
SE
E1
A1 CORNER INDEX MARK 11
10
A
A1
6
b
B
0.15 M Z A B
0.08 M Z
// 0.25 Z
A2
0.08 Z
Z
7
SD
PIN 1 ID.
PACKAGE
JEDEC
SYMBOL
A
A1
A2
D
E
D1
E1
MD
ME
N
b
e
SD / SE
xFBD 048
N/A
6.00 mm x8.00 mm PACKAGE
MIN NOM
MAX
1.10
0.21 0.25
0.29
0.7 0.76
0.82
8.00 BSC
6.00 BSC
5.60 BSC
4.00 BSC
8
6
48
0.30 0.35 0.40
0.80 BSC
0.40 BSC
NOTE
OVERALL THICK
NESS
BALL HEIGHT
BODY THICKNESS
BODY SIZE
BODY SIZE
BALL FOOTPRINT
BALL FOOTPRINT
ROW MATRIX SIZED
DIRECTION
ROW MATRIX SIZED
DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
BALL PITCH
SOLDER BALL
PLACEMENT
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994
2. All dimensions are in millimeters.
3. Ball position designation per JESD 95-1, SPP-010.
4. e represents the solder ball grid pitch.
5. Symbol “MD” is the ball row matrix size in the “D” direction.
Symbol “ME” is the ball column matrix size in the “E” direct-
ion. N is the maximum number of solder balls for matrix si-
ze MD X ME.
6. Dimension “b” is measured at the maximum ball diameter
in a plane parallel to datum Z.
7. SD and SE are measured with respect to datums A and B
and define the position of the center solder ball in the out-
er row. When there is an odd number of solder balls in the
outer row parallel to the D or E dimension, respectively, SD
or SE = 0.000 when there is an even number of solder balls
in the outer row, SD or SE = e/2
8. “X” in the package variations denotes part is outer qualifi-
cation.
9. “+” in the package drawing indicate the theoretical center
of depopulated balls.
10. For package thickness A is the controlling dimension.
11. A1 corner to be indentified by chamfer, ink mark, metalli-
zed markings indention or other means.
ES29LV160E
49
Rev. 0B January 5 , 2006