ES29LV160E Datasheet, PDF (47/53 Pages) Excel Semiconductor Inc. – 16Mbit(2M x 8/1M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory

EE SS II
Excel Semiconductor inc.
Table 20. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1) Max (Note 2) Unit
Comments
Sector Erase Time
Chip Erase Time
0.7
15
sec Excludes 00h programming prior to
erasure (Note 4)
25
sec
Byte Program Time
6
150
us
Word Program Time
Chip Program Time (Note 3)
Byte Mode
Word Mode
8
12.6
8.4
210
us
Exclude system level overhead (Note 5)
37.8
sec
25.2
Notes:
1. Typical program and erase times assume the following conditions: 25^oC, 3.0V Vcc, 10,000 cycles. Additionally, programming
typicals assume checkerboard pattern.
2. Under worst case conditions of 90^oC, Vcc = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
Table 21. LATCHUP CHARACTERISTICS
Description
Input voltage with respect to Vss on all pins except I/O pins (including A9, OE#, and RESET#)
Input voltage with respect to Vss on all I/O pins
Vcc Current
Note: Includes all pins except Vcc. Test conditions: Vcc = 3.0 V, one pin at a time
Min
- 1.0V
- 1.0V
- 100 mA
Max
12.5 V
Vcc + 1.0 V
+100 mA
Table 22. TSOP, SO, AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
C_IN
Input Capacitance
C_OUT
Output Capacitance
C_IN2
Control Pin Capacitance
V_IN = 0
V_OUT = 0
V_IN = 0
Test Setup
TSOP
FBGA
TSOP
FBGA
TSOP
FBGA
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25^oC, f=1.0MHz.
Typ
Max Unit
6
7.5 pF
4.2
5.0 pF
8.5
12 pF
5.4
6.5 pF
7.5
9
pF
3.9
4.7 pF
Table 23. DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
Test conditions
150^oC
125^oC
Min
Unit
10
Years
20
Years
ES29LV160E
47
Rev. 0B January 5 , 2006