XRK69772 Datasheet, PDF (9/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.0
FIGURE 6. OUTPUT-TO-OUTPUT SKEW t_SK(O)
PRELIMINARY
XRK69772
1:12 LVCMOS PLL CLOCK GENERATOR
t_SK(O)
V_CC
V_CC÷2
GND
V_CC
V_CC÷2
GND
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device.
FIGURE 7. PROPOGATION DELAY (t_(Ø), STATIC PHASE OFFSET) TEST REFERENCE
CCLKx
FB_IN
t_(Ø)
V_CC
V_CC÷2
GND
V_CC
V_CC÷2
GND
FIGURE 8. OUTPUT DUTY CYCLE (DC)
tp
T₀
V_CC
V_CC÷2
GND
DC=t_P/T₀ x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
FIGURE 9. I/O JITTER
CCLKx
FB_IN
T_JIT(I/O) = |T₀-T₁mean |
The deviation in t₀ for a controlled edge with respect to a t₀ mean in a random
sample of cycles
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