XRK69772 Datasheet, PDF (8/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

XRK69772
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
3.0 QSYNC TIMING
FIGURE 4. QSYNC TIMING DIAGRAM
REV. P1.0.0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
2
7
8
2
9
3
0
3
1
f_VCO
QA
QC
QSYNC
QA
QC
QSYNC
QC(/2)
QA(/6)
QSYNC
QA(/4)
QC(/6)
QSYNC
QC(/2)
QA(/8)
QSYNC
QA(/6)
QC(/8)
QSYNC
QA(/12)
QC(/2)
QSYNC
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:1 Mode
4:3 Mode
6:1 Mode
XRK69772 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK ) CIRCUITRY
The user can write to the serial input register through the STOP_DATA input by supplying a logic ’0’ start bit
followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the
free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK69772 can
sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any
stop bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by
default, enabled.
FIGURE 5. STOP CLOCK CIRCUIT PROGRAMMING
STOP_CLK
STOP_DATA
START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
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