XRK69772 Datasheet, PDF (6/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

XRK69772
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
TABLE 5: AC CHARACTERISTICS (CON’T) (V_DD = 3.3V +/- 5%)
SYMBOL
CHARACTERISTICS
CONDITION
MIN
TYP
MAX
t_PLZ, t_PHZ
Output Disable Time
8
t_PZL, t_PZH
Output Enable Time
8
t_JIT(CC)
Cycle-to-Cycle Jitter
All outputs in same divider
configuration
150
200
t_JIT(PER)
Period Jitter
All outputs in same divider
150
configuration
t_JIT(I/O)RMS
I/O Jitter (RMS)
÷4 feedback
11
VCO @ 400MHz
÷6 feedback
86
÷8 feedback
13
÷10 feedback
88
÷12 feedback
16
÷16 feedback
19
÷20 feedback
21
÷24 feedback
22
÷32 feedback
27
÷40 feedback
30
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20-3.5
0.70-2.50
0.50-1.80
0.45-1.20
0.30-1.00
0.25-0.70
0.20-0.55
0.17-0.40
0.12-0.30
0.11-0.28
t_LOCK
Max PLL Lock Time
10
NOTES:
a. PLL locked, except when configured in bypass mode.
b. t_(Ø)[s] = t_(Ø)[°] ÷ (fref x 360°)
c. Not including Qsync output
d. T is the output period.
FIGURE 3. TEST LOAD
UNIT
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
Transmission Line
Z = 50Ω
50Ω
V_TT
6