XRK69772 Datasheet, PDF (2/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

XRK69772
PRELIMINARY
1:12 LVCMOS PLL CLOCK GENERATOR
FIGURE 1. BLOCK DIAGRAM OF THE XRK69772
XTAL1
XTAL2
CLK0
CLK1
CLK_SEL
REF_SEL
FB_IN
VCO_SEL
PLL_EN
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
INV_CLK
STOP_DATA
STOP_CLK
MR/OE
XTAL
0
VDD
1
0
1
VDD
Ref
VCO
PLL
200-480MHz
0
÷2 ₀
1
1
FB
DIVIDER SELECT
BANK A
÷4, ÷6,
÷8, ÷12
BANK B
BANK C
÷4, ÷6,
÷8, ÷10
÷2, ÷4,
÷6, ÷8
÷4, ÷6, ÷8,
FB ÷10, ÷12,
÷16, ÷20
Sync Pulse
VDD
VDD
2
2
2
3
POWER-ON RESET
SERIAL
12
INTERFACE
REV. P1.0.0
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
STOP
0
STOP
STOP
1
STOP
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
FIGURE 2. PIN OUT OF THE XRK69772
GND
___
MR/OE
STOP_CLK
STOP_DATA
FSEL_FB2
PLL_EN
REF_SEL
CLK_SEL
CLK0
CLK1
XTAL1
XTAL2
VDD_PLL
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
XRK69772
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
GND
QB0
VDD
QB1
GND
QB2
VDD
QB3
FB_IN
GND
QFB
VDD
FSEL_FB0
2