XRK69772 Datasheet, PDF (3/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.0
PIN DESCRIPTIONS
PRELIMINARY
XRK69772
1:12 LVCMOS PLL CLOCK GENERATOR
PIN #
1, 15, 24, 30,
35, 39, 47, 51
2
NAME
GND
MR/OE
3
4
5, 26, 27
6
7
STOP_CLK
STOP_DATA
FSEL_FB[2:0]
PLL_EN
REF_SEL
8
9,10
11
12
13
14
16, 18, 21, 23
17, 22, 33,
37, 45, 49
19, 20
25
28
29
31
32, 34, 36, 38
40, 41
42, 43
44, 46, 48, 50
52
CLK_SEL
CLK0, CLK1
XTAL1
XTAL2
VDD_PLL
INV_CLK
QC[3:0]
VDD
FSEL_C[1:0]
QSYNC
VDD
QFB
FB_IN
QB[3:0]
FSEL_B[1:0]
FSEL_A[1:0]
QA[3:0]
VCO_SEL
TYPE
POWER Power supply ground
DESCRIPTION
INPUT*
INPUT*
INPUT*
INPUT*
INPUT*
INPUT*
INPUT*
INPUT*
INPUT
OUTPUT
POWER
INPUT*
OUTPUT
POWER
Master reset and output enable. High = output enabled, Low = device
reset & outputs tri-stated
Clock input for serial control.
Data input for serial control
Select inputs for control of feedback divide value.
PLL bypass. High = PLL, Low = PLL bypass
Xtal or CLKx select. High = Xtal input selected, Low = CLK0 or CLK1
selected
CLK0 or CLK1 Select. High = CLK1selected, Low = CLK0 selected
Reference clock inputs.
Crystal oscillator input
Crystal oscillator output
Analog supply for PLL
Invert clock select for QC3 & QC2. High = invert, Low = normal operation
Clock outputs (Bank C)
Power supply for outputs.
INPUT*
OUTPUT
POWER
OUTPUT
INPUT*
OUTPUT
INPUT*
INPUT*
OUTPUT
INPUT*
Bank C divide select pins.
Synchronization output for Bank A and Bank C.
Power supply for core.
Feedback clock output
Feedback input
Clock outputs (Bank B)
Bank B divide select pins.
Bank A divide select pins.
Clock outputs (Bank A)
VCO select. High = VCO/1, Low = VCO/2.
* 25KΩ pull-up resistor
3