XRK69772 Datasheet, PDF (7/12 Pages) Exar Corporation – 1:12 LVCMOS PLL CLOCK GENERATOR

REV. P1.0.0
2.0 CONFIGURATION TABLES
PRELIMINARY
XRK69772
1:12 LVCMOS PLL CLOCK GENERATOR
TABLE 6: FUNCTION CONTROLS
CONTROL PIN
LOGIC 0
LOGIC 1
MR/OE
Resets the output divide circuitry and serial inter-
face, tri-states all outputs
Enables all outputs - normal operation
PLL_SEL
PLL bypass mode enabled. This is a test mode in
which the reference clock is provided to the output
dividers in place of the VCO.
PLL enabled - normal operation
REF_SEL
CLKx selected as ref source to PLL
Crystal Oscillator selected as ref source to PLL.
CLK_SEL
CLK0 selected
CLK1 selected
INV_CLK
QC2 & QC3 are in phase with QC1 & QC4
QC2 & QC3 are 180° out of phase with QC1 & QC4
VCO_SEL
VCO ÷ 2
no divide of VCO
TABLE 7: BANK OUTPUT DIVIDER CONTROLS
INPUT
OUTPUT
INPUT
FSEL_A1 FSEL_A0
QA
FSEL_B1 FSEL_B0
0
0
÷4
0
0
0
1
÷6
0
1
1
0
÷8
1
0
1
1
÷12
1
1
OUTPUT
QB
÷4
÷6
÷8
÷10
INPUT
FSEL_C1 FSEL_C0
0
0
0
1
1
0
1
1
OUTPUT
QC
÷2
÷4
÷6
÷8
TABLE 8: FEEDBACK DIVIDER CONTROL
FSEL_FB2
FSEL_FB1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FSEL_FB0
0
1
0
1
0
1
0
1
QFB
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
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