XRT75R12_15 Datasheet, PDF(86/90 Page) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

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XRT75R12_15 Datasheet, PDF (86/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

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XRT75R12

TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

REV. 1.0.5

TABLE 47: XRT75R12 REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N)

ADDRESS

LOCATION

89 A

C DE F

0x0- APST IER0 ISR0 AS0 TC0 RC0 CC0 JA0 APSR

EM0 EL0 EH0

0X1-

IER1 ISR1 AS1 TC1 RC1 CC1 JA1

EM1 EL1 EH1

0x2-

IER2 ISR2 AS2 TC2 RC2 CC2 JA2

EM2 EL2 EH2

0x3-

IER3 ISR3 AS3 TC3 RC3 CC3 JA3

EM3 EL3 EH3

0x4-

IER4 ISR4 AS4 TC4 RC4 CC4 JA4

EM4 EL4 EH4

0x5-

IER5 ISR5 AS5 TC5 RC5 CC5 JA5

EM5 EL5 EH5

0x6-

CIE CIS

PN VN

0x7-

0x8- APST IER6 ISR6 AS6 TC6 RC6 CC6 JA6 APSR

EM6 EL6 EH6

0X9-

IER7 ISR7 AS7 TC7 RC7 CC7 JA7

EM7 EL7 EH7

0xA-

IER8 ISR8 AS8 TC8 RC8 CC8 JA8

EM8 EL8 EH8

0xB-

IER9 ISR9 AS9 TC9 RC9 CC9 JA9

EM9 EL9 EH9

0xC-

IER10 ISR10 AS10 TC10 RC10 CC10 JA10

EM10 EL10 EH10

0xD-

IER11 ISR11 AS11 TC11 RC11 CC11 JA11

EM11 EL11 EH11

0xE-

CIE CIS

0xF-

TABLE 48: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC

BIT 7

Msb

R/W

BIT 6

R/W

BIT 5

R/W

BIT 4

R/W

BIT 3

R/W

BIT 2

R/W

BIT 1

R/W

BIT 0

Ls bit

R/W

Each channel contains a dedicated 16 bit PRBS error counter. When enabled this counter will accumulate

PRBS errors (as well as excess zeros and LCVs). The LS byte will "carry" a one over to the MS byte each time

it rolls over from 255 to zero until the MS byte also reaches 255. When both counters reach 255, no further

errors will be accumulated and "all ones" will signify an overflow condition.

The counter can be read while in the active count mode. Either register may be read "on the fly" and the other

byte will be simultaneously transferred into the channelâs Error Holding register. The holding register may then

be read to supply the Host with a correct 16 bit count (as of the instant of reading). With this mechanism, the

Host could rapidly cycle thru reading all twelve counters in order (storing the read byte in scratch RAM) and

then come back and read the second byte from each holding register to form the 16 bit accumulation in the

Host system.

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