XRT75R12_15 Datasheet, PDF (64/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.5
TABLE 24: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0
Interrupt Sta- Interrupt Sta- Interrupt Sta- Interrupt Sta- Interrupt Sta- Interrupt Sta-
tus
tus
tus
tus
tus
tus
R/O
R/O
R/O
R/O
R/O
R/O
BIT
NUMBER
7, 6
5
4
3
2
1
0
NAME
Reserved
Channel 5 Interrupt Status
Channel 4 Interrupt Status
Channel 3 Interrupt Status
Channel 2 Interrupt Status
Channel 1 Interrupt Status
Channel 0 Interrupt Status
TYPE
DESCRIPTION
R/O Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT75R12 has a
pending Channel n-related interrupt that is awaiting service. The
first six channels are serviced through this location and the other
six at address 0xE1. These two registers are used by the Host to
identify the source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user's Interrupt Service routine
should be written such that the Microprocessor will now proceed
to read out the contents of the Source Level Interrupt Status Reg-
ister - Channel n (Address Locations = 0xn2) to determine the
exact source of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to
"0" until the user has read out the contents of the Source-
Level Interrupt Status Register bit, that corresponds to the
interrupt request channel.
61