XRT75R12_15 Datasheet, PDF (78/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.5
TABLE 37: XRT75R12 REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_n)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Disable DLOS Disable ALOS RxCLKINV
Detector
Detector
LOSMUT
Enable
Receive
Monitor Mode
Enable
Receive
Equalizer
Enable
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 38: RECEIVE CONTROL REGISTER - CHANNEL n ADDRESS LOCATION = 0XM5
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-6
Reserved
5
Disable DLOS
R/W Disable Digital LOS Detector - Channel_n:
Detector
This READ/WRITE bit-field is used to enable or disable the Digital LOS
(Loss of Signal) Detector within Channel_n, as described below.
0 - Enables the Digital LOS Detector within Channel_n.
1 - Disables the Digital LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been configured to
operate in the DS3 or STS-1 Modes.
4
Disable ALOS
R/W Disable Analog LOS Detector - Channel_n:
Detector
This READ/WRITE bit-field is used to either enable or disable the Analog
LOS (Loss of Signal) Detector within Channel_n, as described below.
0 - Enables the Analog LOS Detector within Channel_n.
1 - Disables the Analog LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been configured to
operate in the DS3 or STS-1 Modes.
3
RxCLKINV
R/W Receive Clock Invert Select - Channel_n:
This READ/WRITE bit-field is used to select the edge of the RxCLK_n out-
put that the Receive Section of Channel_n will use to output the recovered
data via the RxPOS_n and RxNEG_n output pins, as described below.
0 - Configures the Receive Section (within the corresponding channel) to
output the recovered data via the RxPOS_n and RxNEG_n output pins upon
the rising edge of RCLK_n.
1 - Configures the Receive Section (within the corresponding channel) to
output the recovered data via the RxPOS_n and RxNEG_n output pins upon
the falling edge of RCLK_n.
75