XRT75R12_15 Datasheet, PDF (51/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

REV. 1.0.5
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
FIGURE 36. SYNCHRONOUS ΜP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
PCLK
Addr[7:0]
CS
D[7:0]
RD
WR
RDY
READ OPERATION
t₀
Valid Address
WRITE OPERATION
t₀
Valid Address
Valid Data for Readback
t₁
t₂
Data Available to Write Into the LIU
t₃
t₄
SYMBOL
t₀
t₁
t₂
NA
t₃
t₄
NA
TABLE 16: SYNCHRONOUS TIMING SPECIFICATIONS
PARAMETER
Valid Address to CS Falling Edge
MIN
0
-
CS Falling Edge to RD Assert
0
-
RD Assert to RDY Assert
-
35
RD Pulse Width (t₂)
CS Falling Edge to WR Assert
40
-
0
-
WR Assert to RDY Assert
-
35
WR Pulse Width (t₄)
PCLK Period
PCLK Duty Cycle
PCLK "High/Low" time
40
-
15
MAX
UNITS
ns
ns
ns, see note 1
ns
ns
ns, see note 1
ns
ns
NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
time, use the following formula: (PCLK_period * 2) + 5ns
7.3 Register Map
ADDRESS
(HEX)
0x00
0x01
0x02
TABLE 17: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R12
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
REGISTER NAME
CR0
APST R/W APS Transmit Redundancy Control Register 0-5
CR1
CHANNEL 0 CONTROL REGISTERS
IER0
R/W Source Level Interrupt Enable Register - Ch 0
CR2
ISR0 RUR Source Level Interrupt Status Register Ch 0
48