XRT75R12_15 Datasheet, PDF (71/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

REV. 1.0.5
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 32: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-4
Reserved
3
Change of FL Con- RUR Change of FL (FIFO Limit Alarm) Condition Interrupt Status - Ch n:
dition Interrupt Sta-
tus
This RESET-upon-READ bit-field indicates whether or not the Change of FL
Condition Interrupt (for Channel n) has occurred since the last read of this
register.
0 - Indicates that the Change of FL Condition Interrupt has NOT occurred
since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has occurred since
the last read of this register.
NOTE: The user can determine the current state of the FIFO Alarm condition
by reading out the contents of Bit 3 (FL Alarm Declared) within the
Alarm Status Register.(n)
2
Change of LOL Con- RUR Change of Receive LOL (Loss of Lock) Condition Interrupt Status - Ch
dition Interrupt Sta-
n:
tus
This RESET-upon-READ bit-field indicates whether or not the Change of
Receive LOL Condition Interrupt (for Channel n) has occurred since the last
read of this register.
0 - Indicates that the Change of Receive LOL Condition Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Change of Receive LOL Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOL Defect
condition by reading out the contents of Bit 2 (Receive LOL Defect
Declared) within the Alarm Status Register.(n)
1
Change of LOS RUR Change of Receive LOS (Loss of Signal) Defect Condition Interrupt
Condition Interrupt
Status: Ch_n
Status
This RESET-upon-READ bit-field indicates whether or not the Change of the
Receive LOS Defect Condition Interrupt (for Channel n) has occurred since
the last read of this register.
0 - Indicates that the Change of the Receive LOS Defect Condition Interrupt
has NOT occurred since the last read of this register.
1 - Indicates that the Change of the Receive LOS Defect Condition Interrupt
has occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOS Defect
condition by reading out the contents of Bit 1 (Receive LOS Defect
Declared) within the Alarm Status Register.(n)
0
Change of DMO RUR Change of Transmit DMO (Drive Monitor Output) Condition Interrupt
Condition Interrupt
Status - Ch n:
Status
This RESET-upon-READ bit-field indicates whether or not the Change of the
Transmit DMO Condition Interrupt (for Channel n) has occurred since the
last read of this register.
0 - Indicates that the Change of the Transmit DMO Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of the Transmit DMO Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the Transmit DMO
Condition by reading out the contents of Bit 0 (Transmit DMO
Condition) within the Alarm Status Register.(n)
68