XRT75R12_15 Datasheet, PDF (48/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.5
7.0 MICROPROCESSOR INTERFACE BLOCK
The Microprocessor Interface section supports communication between the local microprocessor (µP) and the
LIU. The XRT75R12 supports a parallel interface asynchronously or synchronously timed to the LIU. The
microprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor
interface mode is shown in Table 13.
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE
PMODE
MICROPROCESSOR MODE
"Low"
Asynchronous Mode
"High"
Synchronous Mode
The local µP configures the LIU by writing data into specific addressable, on-chip Read/Write registers. The
µP provides the signals which are required for a general purpose microprocessor to read or write data into
these registers. The µP also supports polled and interrupt driven environments. A simplified block diagram of
the microprocessor is shown in Figure 34.
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
CS
WR
RD
Addr[7:0]
D[7:0]
PCLK
Pmode
RESET
RDY
INT
Microprocessor
Interface
7.1 The Microprocessor Interface Block Signals
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are
described below in Table 14. The microprocessor interface can be configured to operate in Asynchronous
mode or Synchronous mode.
PIN NAME
Pmode
D[7:0]
Addr[7:0]
TABLE 14: XRT75R12 MICROPROCESSOR INTERFACE SIGNALS
TYPE
DESCRIPTION
I Microprocessor Interface Mode Select Input pin
This pin is used to specify the microprocessor interface mode.
I/O Bi-Directional Data Bus for register "Read" or "Write" Operations.
I Eight-Bit Address Bus Inputs
The XRT75R12 LIU microprocessor interface uses a direct address bus. This address bus is
provided to permit the user to select an on-chip register for Read/Write access.
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