XRT75R12_15 Datasheet, PDF (2/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.5
FEATURES
RECEIVER
 R³ Technology (Reconfigurable, Relayless
Redundancy)
 On chip Clock and Data Recovery circuit for high
input jitter tolerance
 Meets E3/DS3/STS-1 Jitter Tolerance Requirement
 Detects and Clears LOS as per G.775
 Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
 On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
 On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
 Provides low jitter output clock
TRANSMITTER
 R³ Technology (Reconfigurable, Relayless
Redundancy)
 Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
 Each channel supports Analog, Remote and Digital
Loop-backs
 Single 3.3 V ± 5% power supply
 5 V Tolerant digital inputs
 Available in 420 pin TBGA Thermally enhanced
Package
 - 40°C to 85°C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
 Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
 Integrated Pulse Shaping Circuit
 Built-in B3ZS/HDB3 Encoder (which can be
disabled)
 Accepts Transmit Clock with duty cycle of 30%-
70%
 Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications
 Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
 Tri-state Transmit output capability for redundancy
applications
 Each Transmitter can be independently turned on
or off
 Transmitters provide Voltage Output Drive
JITTER ATTENUATOR
 On chip advanced crystal-less Jitter Attenuator for
each channel
 Jitter Attenuator can be selected in Receive,
Transmit path, or disabled
 Meets ETSI TBR 24 Jitter Transfer Requirements
 Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
 16 or 32 bits selectable FIFO size
CONTROL AND DIAGNOSTICS
 Parallel Microprocessor Interface for control and
configuration
 Supports optional internal Transmit driver
monitoring
 Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE
 Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
 Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
 Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
 Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
 Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
 Declares Loss of Lock (LOL) Alarm
 Built-in B3ZS/HDB3 Decoder (which can be
disabled)
 Recovered Data can be muted while the LOS
Condition is declared
 Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
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