XRT75L04D Datasheet, PDF (8/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L04D
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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
52
TxON_0
49
TxON_1
169
TxON_2
172
TxON_3
I Transmitter ON Input - Channel 0:
Transmitter ON Input - Channel 1:
Transmitter ON Input - Channel 2:
Transmitter ON Input - Channel 3:
These pins are active only when the corresponding TxON bit is set.
Table below shows the status of the transmitter based on theTxON bit and
TxON pin settings.
46
TxCLK_0
34
TxCLK_1
175
TxCLK_2
11
TxCLK_3
44
TNEG_0
32
TNEG_1
1
TNEG_2
13
TNEG_3
Host/HW
Bit
1
0
1
0
1
1
1
1
0
x
0
x
Pin
Transmitter Status
0
OFF
1
OFF
0
OFF
1
ON
0
OFF
1
ON
NOTES:
1. These pins will be active and can control the TTIP and TRING outputs
only when the TxON_n bits in the channel register are set .
2. When Transmitters are turned off the TTIP and TRING outputs are Tri-
stated.
3. These pins are internally pulled up.
I Transmit Clock Input for TPOS and TNEG - Channel 0:
Transmit Clock Input for TPOS and TNEG - Channel 1:
Transmit Clock Input for TPOS and TNEG - Channel 2:
Transmit Clock Input for TPOS and TNEG - Channel 3:
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
By default, input data is sampled on the falling edge of TxCLK when input data
is changing on the rising edge of TxCLK..
I Transmit Negative Data Input - Channel 0:
Transmit Negative Data Input - Channel 1:
Transmit Negative Data Input - Channel 2:
Transmit Negative Data Input - Channel 3:
In Dual-rail mode, these pins are sampled on the falling or rising edge of
TxCLK_n .
NOTES:
1. These input pins are ignored and must be grounded if the Transmitter
Section is configured to accept Single-Rail data from the Terminal
Equipment.
4