XRT75L04D Datasheet, PDF (17/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L04D
REV. 1.0.1 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
OPERATING MODE SELECT
92
E3_0
101
E3_1
129
E3_2
120
E3_3
I
E3 Mode Select Input
A "High" on this pin configures Channel_n to operate in E3 mode.
A "Low" on this pin configures Channel_n to operate in either STS-1 or DS3
mode depending on the settings on pins 93,102,128 and 119 pins.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and should be tied to GND if configured to operate
in HOST mode.
93
STS-1/DS3_0
102
STS-1/DS3_1
128
STS-1/DS3_2
119
STS-1/DS3_3
I
STS-1/DS3 Select Input
A “High” on these pins configures the Channel_n to operate in STS-1 mode.
A “Low” on these pins configures the Channel_n to operate in DS3 mode.
These pins are ignored if the E3_n pins are set to “High”.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and should be tied to GND if configured to operate
in HOST mode.
136
SR/DR
I
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, TNEG_n pin should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
SERIAL MICROPROCESSOR INTERFACE
86
CS
RxCLKINV
88
SClk
TxCLKINV
I
Microprocessor Serial Interface - Chip Select
Toggle this pin “Low” to enable the communication with the Microprocessor
Serial Interface.( see figures 10 & 11)
NOTE: If configured in Hardware Mode, this pin functions as RxClkINV.
I
Serial Interface Clock Input
The data on the SDI pin is sampled on the rising edge of this signal. Addition-
ally, during Read operations the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
NOTE: If configured in Hardware Mode, this pin functions as TxClkINV.
87
SDI
RxON
I
Serial Data Input:
Data is serially input through this pin.
The input data is sampled on the rising edge of the SClk pin (pin 88).
NOTES:
1. This pin is internally pulled down
2. If configured in Hardware Mode, this pin functions as RxON.
85
SDO
RxMON
I/O Serial Data Output:
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data is updated on the falling edge of the SClk and this
pin is tri-stated upon completion of data transfer.
NOTE: If configured in Hardware Mode, this pin functions as RxMON.
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