XRT75L04D Datasheet, PDF (42/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L04D
áç
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
of overflowing or underflowing, the FIFO limit status bit, FL_n is set to “1” in the Alarm status register. Reading
this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter. Table 13 specifies the jitter transfer mask requirements for various data rates:
TABLE 13: JITTER TRANSFER PASS MASKS
RATE
(KBITS)
MASK
F1
F2
F3
F4
A1(dB)
A2(dB)
(HZ)
(HZ)
(HZ)
(KHZ)
G.823
100
300
34368
ETSI-TBR-24
3K
800K
0.5
-19.5
44736
GR-499, Cat I
10
10k
-
15k
0.1
-
GR-499, Cat II
10
56.6k
-
300k
0.1
-
GR-253 CORE
10
40
-
15k
0.1
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
The jitter attenuator in the XRT75L04D meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
A1
A2
F1
F2
F3
F4
JIT T E R F R E Q U E N C Y (kH z)
38