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XRT75L04D Datasheet, PDF (18/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04D
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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
SERIAL MICROPROCESSOR INTERFACE
84
INT
LOSMUT
I/O INTERRUPT Output:
This pin functions as Interrupt Output for Serial Interface. A transition to “Low”
indicates that an interrupt has been generated by the Serial Interface. The inter-
rupt function can be disabled by setting the interrupt enable bit to “0” in the
Channel Control Register.
NOTES:
1. In Hardware mode, this pin functions as LOSMUT.
2. This pin will remain asserted “Low” until the interrupt is serviced.
133
RESET
I Register Reset:
Setting this input pin "Low" causes the XRT75L04D to reset the contents of the
Command Registers to their default settings and default operating configuration
NOTE: This pin is internally pulled up.
JITTER ATTENUATOR INTERFACE
PIN #
154
SIGNAL NAME
JA1
TYPE
I
DESCRIPTION
Jitter Attenuator Select 1:
In Hardware Mode, this pin along with the pin JA0 configures the Jitter Attenua-
tor as shown in the table.
155
JATx/Rx
153
JA0
JA0
JA1
Mode
0
0
16 bit FIFO
0
1
32 bit FIFO
1
0
128 bit FIFO
1
1
Disable Jitter
Attenuator
NOTE: This pin is internally pulled down.
I
Jitter Attenuator Path Select
In Hardware Mode, tie this pin “High” to select the Jitter Attenuator in the Trans-
mit Path . Connect this pin “Low” to select the Jitter Attenuator in the Receive
Path. This applies to all4 channels.
NOTE: This pin is internally pulled down.
I
Jitter Attenuator Select 0:
In Hardware Mode, this pin along with pin 154 configures the Jitter Attenuator
as shown in the above table f.
NOTE: This pin is internally pulled down.
ANALOG POWER AND GROUND
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
43
TxAVDD_0
**** Transmitter Analog 3.3 V ± 5% VDD - Channel 0
31
TxAVDD_1
**** Transmitter Analog 3.3 V ± 5% VDD - Channel 1
14