XRT75L04D Datasheet, PDF (48/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

XRT75L04D
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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMO_n This bit is set when no transitions on the TTIP/
0
TRING have been detected for 128 ± 32 TxCLK
periods.
D1 RLOS_n This bit is set every time the receiver declares an
0
LOS condition.
D2 RLOL_n This bit is set every time when the receiver declares
0
a Loss of Lock condition.
D3
FL_n This bit is set every time the FIFO in the Jitter Atten-
0
uator is within 2 bit of underflow/overflow condition.
D4 ALOS_n This bit is set every time the receiver declares Ana-
0
0x03 (ch 0) Read Alarm Sta-
log LOS condition.
0x0B (ch 1) ^{Only tus}
0x13 (ch 2)
D5 DLOS_n This bit is set every time the receiver declares Digital
0
LOS condition.
0x1B (ch 3)
D6 PRBSLS_n This bit is set every time the PRBS detector is not in
0
sync.
D7
Reserved
D0 TxLEV_n ^{Set this bit for cable length greater than 225} 0
feet.
NOTE: See section 4.03 for detailed description.
D1 TxClkINV_ Set this bit to sample the data on TPOS/TNEG pins
0
n
on the rising edge of TxClk.
D2 TAOS_n Set this bit to send a continuous stream of marks
0
(All Ones) out at the TTIP and TRing pins.
0x04 (ch 0) R/W Transmit
D3
Reserved
0x0C (ch 1)
0x14 (ch 2)
Control
D4 INSPRBS_ Setting this bit causes the PRBS generator to insert
0
n
a single-bit error onto the transmit PRBS data
0x!C (ch 3)
stream .
NOTE: PRBS Generator/Detector must be enabled
for this bit to have any effect.
D5 TxMON_n Setting this bit causes the driver monitor its own
0
transmit driver. When the transmit failure is
detected, DMO output pin goes “High” and DMOIS
bit is set.
When this bit is “0”, MTIP and MRing are connected
to other transmit channel for monitoring.
D7-D6
Reserved
44