XRT75L04D Datasheet, PDF (47/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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XRT75L04D
REV. 1.0.1 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMOIE_n Set this bit to enable an interrupt when the no trans-
0
mission detected on channel output.
D1 RLOSIE_n Writng a “1” to this bit enables an interrupt when
0
Recieve Los of Signal is detected.
D2 RLOLIE_n Writing a “1” to this bit enables an interrupt when
0
Receive Loss of Lock condition is detected
0x01 (ch 0) R/W Interrupt
D3 FLIE_n Writing a “1” to this bit enables the interrupt when
0
0x09 (ch 1)
0x11 (ch 2)
0x19 (ch 3)
Enable
(source
level)
the FIFO Limit of the Jitter Attenuator is within 2 bits
of overflow/underflow condition.
NOTE: This bit field is ignored when the Jitter
Attenuator is disabled.
D4 PRBSERIE Set this bit to enable the interrupt when the PRBS
0
_n
error is detected.
D5 PRBSERC Set this bit to enable the interrupt when the PRBS
0
NTIE_n error count register saturates.
D7-D6
Reserved
D0 DMOIS_n This bit is set every time a DMO status change has
0
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
D1 RLOSIS_n This bit is set every time a RLOS status change has
0
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
D2 RLOLIS_n This bit is set every time a RLOL status change has
0
0x02 (ch 0) Reset Interrupt
occurred since the last cleared interrupt. This bit is
0x0A (ch 1) ^{on Status}
cleared when the register bit is read.
0x12 (ch 2) ^{Read (source}
level)
0x1A (ch 3)
D3 FLIS_n This bit is set every time a FIFO Limit status change
0
has occurred since the last cleared interrupt. This bit
is cleared when the register bit is read.
D4
This bit is set when the PRBS error occurs.
0
PRBSERIS
_n
D5 PRBSERC This bit is set when the PRBS error count register
0
NTIS_n saturates.
D7-D6
Reserved
43