XRT75L04D Datasheet, PDF (6/98 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

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FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
FIGURE 36. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE ......... 60
FIGURE 37. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN
STS-1 SPE.......................................................................................................................................................................... 60
9.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 61
9.2.2.1 THE IDEAL CASE FOR MAPPING DS3 DATA INTO AN STS-1 SIGNAL (E.G., WITH NO FREQUENCY OFFSETS) ............ 62
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .................................... 62
9.2.2.2 THE 44.736MBPS + 1PPM CASE ........................................................................................................................... 63
FIGURE 39. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL
THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL .................................................................................. 63
9.2.2.3 THE 44.736MBPS - 1PPM CASE ............................................................................................................................ 64
9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................... 65
9.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 65
FIGURE 40. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL
THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL ................................................................................... 65
FIGURE 41. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES ........................................... 66
9.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK .................................................................................. 67
FIGURE 42. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF
THE J1 BYTE, DESIGNATED .................................................................................................................................................... 67
FIGURE 43. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES)
AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME .................................................. 67
9.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................... 68
FIGURE 44. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER.................................................................... 69
FIGURE 45. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DES-
IGNATED ............................................................................................................................................................................... 70
FIGURE 46. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DES-
IGNATED ............................................................................................................................................................................... 71
9.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................... 72
9.4 CLOCK GAPPING JITTER ............................................................................................................................. 72
FIGURE 47. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION ........................................ 72
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS ............................................................................................................................. 73
TABLE 22: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS ........ 73
9.5.1 DS3 DE-MAPPING JITTER......................................................................................................................................... 74
9.5.2 SINGLE POINTER ADJUSTMENT ............................................................................................................................. 74
9.5.3 POINTER BURST........................................................................................................................................................ 74
FIGURE 48. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO................................................................................................ 74
9.5.4 PHASE TRANSIENTS................................................................................................................................................. 75
FIGURE 49. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ........................................................................................... 75
FIGURE 50. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO ............................................................................ 75
9.5.5 87-3 PATTERN............................................................................................................................................................ 76
9.5.6 87-3 ADD ..................................................................................................................................................................... 76
FIGURE 51. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN .................................................................... 76
9.5.7 87-3 CANCEL .............................................................................................................................................................. 77
FIGURE 52. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN....................................................................................... 77
FIGURE 53. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO ...................................................................................... 77
9.5.8 CONTINUOUS PATTERN........................................................................................................................................... 78
9.5.9 CONTINUOUS ADD ................................................................................................................................................... 78
FIGURE 54. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO ...................................................................... 78
9.5.10 CONTINUOUS CANCEL ........................................................................................................................................... 79
FIGURE 55. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO ............................................................................... 79
FIGURE 56. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO ......................................................................... 79
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. .................................. 80
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION ................................................................................................................................................ 80
9.7.1 INTRINSIC JITTER TEST RESULTS.......................................................................................................................... 80
TABLE 23: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ........................................... 80
9.7.2 WANDER MEASUREMENT TEST RESULTS............................................................................................................ 81
9.8 DESIGNING WITH THE LIU ........................................................................................................................... 81
9.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS............................................................................................................. 81
FIGURE 57. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS ................................ 81
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06..................................................................... 82
CHANNEL 1 ADDRESS LOCATION = 0X0E ............................................................ 82
CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................................. 82
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06..................................................................... 83
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