XR68C92_05 Datasheet, PDF (8/33 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
while the XR68C92/192 has an interrupt pending, the
XR68C92/192 will place the contents of the interrupt
vector register (IVR, address 0x0C) on the data bus
and assert the data transfer acknowledge signal
(-DACK). If the XR68C92/192 has no pending inter-
rupt, it ignores the -IACK cycles. In addition, users can
program the parallel outputs OP3 through OP7 to
provide discrete interrupt outputs for the transmitters,
the receivers, and the C/T. See 'Multi-purpose Out-
puts' section for details.
DATA BUS BUFFER (D0 - D7)
The data bus buffer provides the interface between the
external and internal data buses. It is controlled by the
internal control logic to allow read and write data
transfer operations to occur between the controlling
CPU and XR68C92/192 by way of the eight parallel
data lines (D0 through D7).
MULTI-PURPOSE INPUTS (IP0 - IP5)
The states of the seven multi-purpose inputs (IP0
through IP5) can be read from the internal register IPR
(address 0x0D). The bits in this register are the
complements of the actual inputs - for example, if the
IP0 is low, the corresponding bit in the IPR, bit-0 is a
logic '1'. Each of these inputs also has an alternate
control function capability. The alternate functions can
be enabled/disabled on a bit-by-bit basis. The table
below shows how each of these inputs is configured for
its special function.
Four change-of-state detectors are associated with
inputs IP0, IP1, IP2, and IP3. If a high-to-low or low-to-
high transition occurs on any of these inputs, the
corresponding bit in the input port change register
(IPCR - address 0x04) will be set accordingly. The
sampling clock of the change detectors is the XTAL1/
96 tap of the baud rate generator, which is 38.4kHz if
XTAL1 is 3.6864MHz. A new input level must be
Input Function
Programming
IP0 -CTSA
Set MR2A bit-4 = 1
IP1 -CTSB
Set MR2B bit-4 = 1
IP2 C/T Ext. Clk Set ACR[6:4] = 000
IP3 TxA Ext. Clk Set CSRA[3:0] = 1110 or 1111
IP4 RxA Ext. Clk Set CSRA[7:4] = 1110 or 1111
IP5 TxB Ext. Clk Set CSRB[3:0] = 1110 or 1111
sampled on two consecutive sampling clocks to detect
a change. Also, users can program the XR68C92/192
to allow a change of state in any of the inputs IP0
through IP3 to generate an interrupt to the CPU. See
description of the Interrupt Status Register (ISR, ad-
dress 0x05) for details. The IPCR bits are cleared when
the CPU reads the register. Also see the Baud Rate
Table on page 18.
MULTI-PURPOSE OUTPUTS (OP0 - OP7)
The eight output pins (OP0 - OP7) can either be used
as general purpose outputs or can be used for alter-
nate functions representing various conditions using
- Mode Registers 1 and 2 (MR1A, MR1B, MR2A,
MR2B)
- Output Port Configuration Register (OPCR)
- Set Output Port Register (SOPR), and
- Reset Output Port Register (ROPR).
OP0 and OP1:
The output OP0 can function as the channel A request-
to-send (-RTSA) output for either the transmitter
(MR2A bit-5 = 1) or the receiver (MR1A bit-7 = 1). Note
that only one of these bits should be set to '1' at a given
time. See the description of the transmitter RTS and
receiver RTS in the 'Transmitter' and 'Receiver' sec-
tions of this datasheet respectively. The output OP1
acts as the channel B request-to-send (-RTSB) output
XR68C92/192
200 - 500 kΩ
XTAL1
XTAL2
Y1
3.6864MHz
C1
22-47pF
C2
22-47pF
Figure 1: Crystal Connection
Rev. 1.33
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