XR68C92_05 Datasheet, PDF (3/33 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

Block Diagram
D0-D7
R/-W
-DTACK
-IACK
-RESET
A0-A3
-CS
-INT
XTAL1
XTAL2
Rev. 1.33
XR68C92/192
Channel A
Transmit
FIFO
Registers
Transmit
Shift
Register
Flow
Control
Logic
Receive
FIFO
Registers
Receive
Shift
Register
Flow
Control
Logic
Watch
Dog
Timer
Channel B
Transmit
FIFO
Registers
Transmit
Shift
Register
Flow
Control
Logic
Receive
FIFO
Registers
Flow
Control
Logic
Receive
Shift
Register
Watch
Dog
Timer
Multi-
Purpose
I/O
Control
Logic
TXA
RXA
TXB
RXB
OP0-OP7
IP0-IP5
3