XR68C92_05 Datasheet, PDF (13/33 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
dress 0x7) can be from 0x0001 through 0xFFFF and can
be changed at any time. At power-up and after reset, the
C/T operates in counter mode.
COUNTER MODE
In counter mode, the CPU can start and stop the C/T.
This mode allows the C/T to function as a system
stopwatch or a real-time single interrupt generator. In
this mode, the C/T counts down from the pre-load
value using the programmed counter clock source.
When a read at the start counter command register
(address 0xE) is performed, the counter is initialized to
the pre-load value and begins a countdown sequence.
When the counter counts from 0x0001 to 0x0000
(terminal count), the C/T-ready bit in the interrupt
status register (ISR Bit-3) is set.
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Users can program the counter to generate an inter-
rupt request for this condition on the -INT output by
unmasking the bit-3 in the Interrupt Mask Register
(IMR, address 0x5). After 0x0000 the count becomes
0xFFFF, and the counter continues counting down
from there. If the CPU changes the pre-load value, the
counter will not recognize the new value until it receives
the next start counter command (and is reinitialized).
When a read at the stop counter command register
(address 0xF) is performed, the counter stops the
countdown sequence and clears ISR Bit-3. The count
value should only be read while the counter is stopped
because only one of the count registers (either CUR, at
address 0x6 or CLR, at address 0x7) can be read at a
time. If the counter is running, a decrement of CLR that
requires a borrow from the CUR could take place
between the two register reads. Figure 2 shows the
C/T output in the counter mode. OP3 can be pro-
grammed to show the C/T output.
In addition to the watch dog timer described above, the
C/T can be used for receive timeout function (see
description under CRA, CRB in the registers section
also). The C/T is more accurate and the timeout period
is programmable unlike the watchdog timer. However,
only one channel can use the C/T for receive timeout
at any given time. The C/T timeout mode uses the
received data stream to start the counter. Each time a
character is shifted from the receive shift register to the
receive FIFO, the C/T is reloaded with the pro-
grammed value in CTPU and CTPL and it restarts on
the next C/T clock. If a new character is not received
before the C/T reaches terminal count (= 0x0000), a
counter ready interrupt (ISR bit-3) is generated. The
user can appropriately program the CTPU and CTPL
for the desired timeout period. Typically this is slightly
more than one character time. Note that if C/T is used
for receiver timeout, a counter ready interrupt is gener-
ated whereas if the watchdog timer is used, a receiver
ready interrupt is generated.
TIMER MODE
In the timer mode, the C/T runs continuously once the
start command is issued (by reading the start C/T
START C/T COMMAND
ISSUED
PRELOAD TERMINAL PRELOAD TERMINAL PRELOAD TERMINAL PRELOAD
VALUE COUNT VALUE COUNT VALUE COUNT
VALUE
C/T OUTPUT IN
TIMER MODE
PRELOAD TERMINAL PRELOAD TERMINAL PRELOAD TERMINAL
VALUE COUNT
VALUE COUNT
VALUE COUNT
PRELOAD TERMINAL
VALUE COUNT
C/T OUTPUT IN
COUNTER MODE
Rev. 1.33
Figure 2: C/T output in Timer and Counter modes.
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