XR68C92_05 Datasheet, PDF (20/33 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
0 1 1 0 = Start Break. Forces the transmitter output to
go low and stay low. If transmitter is empty
the start of the break condition will be de-
layed up to two bit times. If transmitter is
active, all the characters in the FIFO are
transmitted before break signal is sent.
Transmitter must to be enabled for this
command to work.
0 1 1 1 = Stop Break. Transmit output will go high
within two bit times.
1 0 0 0 = Set -RTS output to low (assertion).
1 0 0 1 = Reset -RTS output to high (negation).
1 01 0 = Set Timeout Mode On. The receiver in this
channel will restart the C/T as each receive
character is transferred from the shift regis-
ter to the receive FIFO. The C/T is placed in
the counter mode, the START/STOP
counter commands are disabled, the
counter is stopped, and the Counter Ready
Bit, ISR Bit-3 is reset. (See also Watchdog
timer description)
1 0 1 1 = Set MR pointer to MR0.
1 1 0 0 = Disable Timeout Mode. This command re-
turns control of the C/T to the regular Start/
Stop counter commands. It does not stop
the counter or clear any pending interrupts.
After disabling the timeout mode, a “Stop
Counter” command should be issued to
force a reset of the ISR Bit-3.
1 1 0 1 = Not used.
1 1 1 0 = Enable Power Down Mode. In this mode, the
DUART oscillator is stopped and all func-
tions requiring this clock are suspended.
The execution of commands other than dis-
able power down mode (1111) requires a
XTAL1. While in the power down mode, do
not issue any commands to the CRA or CRB
except the disable power down mode com-
mand. The contents of all registers will be
saved while in this mode. It is recommended
that the transmitter and receiver be disabled
prior to placing the DUART into power down
mode. This command is in CRA only.
1 1 1 1 = Disable Power Down Mode. This command
restarts the oscillator. After invoking this
command, wait for the oscillator to start up
before writing further commands to the CR A/
B. For maximum power reduction all input
pins should be at GND or VCC. This com-
mand is in CRA only.
RECEIVE BUFFER (RXA, RXB)
The receive buffer consists of a 8-characters deep FIFO
in XR68C92 and 16-characters deep FIFO in XR68C192.
The received characters are transferred from the shift
register one at a time to the FIFO and are stored there
until read by the CPU or flushed by a reset receiver
command.
TRANSMIT BUFFER (TXA, TXB)
The transmit buffer consists of a 8-characters deep
FIFO in XR68C92 and 16-characters deep FIFO in
XR68C192. Once loaded in the FIFO, the characters
are transferred to the transmit shift register one at a
time and transmitted unless the transmitter is disabled.
INPUT PORT CHANGE REGISTER (IPCR)
This is a read-only register which gives the state and
the change-of-state information of the multi-purpose
inputs IP0, IP1, IP2 and IP3.
IPCR Bits 3-0: Levels of IP3 - IP0.
These show the current state of IP3, IP2, IP1 and IP0
respectively.
0 = Low
1 = High
IPCR Bits 7-4: Transitions of IP3 - IP0.
These indicate if there has been a change of state in
IP3, IP2, IP1 and IP0 respectively. They are cleared
when the register is read by the CPU.
0 = No
1 = Yes
AUXILIARY CONTROL REGISTER (ACR)
ACR Bits 3-0:
This field selects which bits of the input port change
register (IPCR) cause the interrupt status register
(ISR) bit-7 to be set. For example, if bit-0 = 1, then a
change of state in IP0 will set ISR bit-7. If bit-0 and bit-
2 are both '1', then whenever IP0 or IP2 changes state,
ISR bit-7 will be set.
0 = Disabled (default)
1 = Enabled
ACR Bits 6-4:
Counter/Timer Mode and Clock Source. These bits
should not be altered while the C/T is in use. Prior to
changing these bits, the C/T must be stopped if in
counter mode. If the C/T is in timer mode, its output
Rev. 1.33
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