XR68C92_05 Datasheet, PDF (23/33 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
OP5 output select (Bit 5):
0 = Controlled by SOPR and ROPR (default)
1 = -RxBRDY which is the complement of ISR bit-5
OP6 output select (Bit 6):
0 = Controlled by SOPR and ROPR (default)
1 = -TxARDY which is the complement of ISR bit-0
OP7 output select (Bit 7):
0 = Controlled by SOPR and ROPR (default)
1 = -TxBRDY which is the complement of ISR bit-4
START COUNTER/TIMER REGISTER (STCR) -
Read Only
Reading from this register will start the C/T. Data
values returned should be ignored.
STOP COUNTER/TIMER REGISTER (SPCR) -
Read Only
Reading from this register will stop the C/T. Data
values returned should be ignored.
SET OUTPUT PORT REGISTER (SOPR) -
Write Only
Output ports (OP0-OP7), when used as general pur-
pose outputs, can be asserted (set to low) by writing a
“1” to the corresponding bit in this register. Once an
output is asserted, it can be negated only by issuing a
command through the Reset Output Port Register (see
below).
However, note that SOPR and ROPR cannot be used
to assert and negate outputs that are programmed for
alternate functions (see description under OPCR). For
example, if OP0 is programmed to output -RTSA (see
'Configuring Multi-purpose Outputs), it cannot be con-
trolled by SOPR or ROPR. In that case, commands
from the Command Register should be issued to
assert (CRA bits 7:4 = 0x8) and negate (CRA bits 7:4
= 0x9) OP0.
SOPR Bit 0-7:
0 = No change (same state).
1 = Assert the corresponding output (Set it low).
RESET OUTPUT PORT REGISTER (ROPR) - Write
Only
Each output port bit can be changed to high state by
writing a “1” to each individual bit.
ROPR Bit 0-7:
0 = No change (same state).
1 = Negate the corresponding output (Set it high).
Rev. 1.33
23