XR68C92_05 Datasheet, PDF (21/33 Pages) Exar Corporation – DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

XR68C92/192
must be disabled and its interrupt must be masked. The
following table shows how to select the clock source for
the C/T when used in counter mode or timer mode:
ACR Bit-7: Baud rate table Select.
This bit is used to select between two sets of baud rate
tables. See Baudrate table on Page 18. It should be
changed only after both channels have been reset and
disabled.
0 = Set 1
1 = Set 2
ACR
C/T
Bits 6:4 Mode
000
001
010
011
Counter
Counter
Counter
Counter
100
101
110
Timer
Timer
Timer
1 1 1 Timer
Clock Source
External (IP2)
TXAClk1-Transmit A 1X clock
TXBClk1-Transmit B 1X clock
Crystal or External Clock
(XTAL1/Clk) Divided by 16
External (IP2)
External (IP2) Divided by 16
Crystal or External Clock
(XTAL1/Clk)
Crystal or External Clock
(XTAL1/Clk) Divided by 16
INTERRUPT STATUS REGISTER (ISR)
This register provides the status of all potential interrupt
sources. The contents of this register are logically
“AND”-ed with the contents of the interrupt mask
register, and the results are “OR”-ed. The resulting
signal is inverted to produce the -INT output. All active
interrupt sources are visible by reading the ISR, re-
gardless of the contents of the interrupt mask register.
Reading the ISR has no effect on any interrupt source.
Each active interrupt source must be cleared in a
source-specific fashion to clear the ISR. All interrupt
sources are cleared when the XR68C92/192 is reset.4
ISR Bit-0: Transmit ready A.
This bit is set when channel A's transmit buffer (FIFO)
is filled below the programmed transmit trigger level
(see MR0A bits 5-4). For example, if a TX trigger level
of '4' is chosen, this bit will be set whenever the TX
FIFO has four or more empty locations. This bit can be
cleared by loading the TX FIFO above the trigger level.
ISR Bit-1: Receive ready A .
This bit is set when channel A's receive buffer (FIFO) is
filled above the programmed receive trigger level condi-
tion (see MR0A bit-6 and MR1A bit-6). For example, if
a RX trigger level of '6' is chosen, this bit will be set
whenever the RX FIFO contains six or more bytes. This
bit can be cleared by reading the data out of the FIFO
till it falls below the trigger level.
ISR Bit-2: Channel A change in break.
This bit is set when channel A receiver detects the
beginning or the end of a break condition. It is reset
when the CPU issues a channel A reset break change
interrupt command (CRA bits 7-4 = 0x5).
ISR Bit-3: Counter/Timer (C/T) ready.
In counter mode, this bit is set when the C/T reaches
terminal count. In timer mode, this bit is set each time
the C/T output switches from low to high (rising edge -
see Figure 2). In either mode, this bit is cleared by a
stop counter command.
ISR Bit-4: Transmit ready B.
This bit is set when channel B's transmit buffer (FIFO)
is filled below the programmed transmit trigger level
(see MR0B bits 5-4). For example, if a TX trigger level
of '4' is chosen, this bit will be set whenever the TX
FIFO has four or more empty locations. This bit can be
cleared by loading the TX FIFO above the trigger level.
ISR Bit-5: Receive ready B.
This bit is set when channel B's receive buffer (FIFO)
is filled above the programmed receive trigger level
condition (see MR0B bit-6 and MR1B bit-6). For ex-
ample, if a RX trigger level of '6' is chosen, this bit will
be set whenever the RX FIFO contains six or more
bytes. This bit can be cleared by reading the data out
of the FIFO till it falls below the trigger level.
ISR Bit-6. Channel B change in break.
This bit is set when channel B receiver detects the
beginning or the end of a break condition. It is reset
when the CPU issues a channel B reset break change
interrupt command (CRB bits 7-4 = 0x5).
ISR Bit-7. Input port change status.
This bit is set when a change of state has occurred at
the IP0, IP1, IP2, or IP3 inputs, and that event has been
enabled to cause an interrupt by programming ACR
Bits 3-0. This bit is cleared when the CPU reads the
input port change register.
Rev. 1.33
21