XR17C154 Datasheet, PDF (8/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

XR17C154
5V PCI BUS QUAD UART
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REV. 1.3.0
SPACE,
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS BITS
TYPE
0x00
0x04
31:16 _RWR¹
15:0 _RWR¹
31:28 RO
27
R-Reset
26:25 RO
24
RO
23
RO
22:16 RO
15:9,7, RO
5,4,3,2
8
WO
6
WO
1
RWR
0
RO
0x08
0x0C
0x10
0x14
0x18h
0x1C
0x20
0x24
0x28
31:8 RO
7:0
RO
31:24 RO
23:16 RO
15:8 RO
7:0
RO
31:11 RW
10:0 RO
31:0 RO
31:0 RO
31:0 RO
31:0 RO
31:0 RO
31:0 RO
DESCRIPTION
Device ID (Exar device ID number or from EEPROM)
Vendor ID (Exar ID or from EEPROM) specified by PCISIG
Status bits (error reporting bits)
Target Abort. Set whenever 154 terminates with a target abort.
DEVSEL# timing.
Unimplemented bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bits
Command bits (reserved)
RESET VALUE
(HEX)
0x0154
0x13A8
0000
0
00
0
1
000 0000
0x0000
SERR# driver enable. Logic 1=enable driver and 0=disable
0
driver
Parity error enable. Logic 1=respond to parity error and 0=ignore
0
Command controls a device’s response to mem space accesses:
0
0=disable mem space accesses, 1=enable mem space accesses
Command controls a device’s response to I/O space accesses:
0
0 = disable I/O space accesses 1 = enable I/O space accesses
Class Code (Simple 550 Communication Controller).
0x070002
Revision ID (Exar device revision number)
Current Rev. value
BIST (Built-in Self Test)
0x00
Header Type (a single function device with one BAR)
0x00
Unimplemented Latency Timer (needed only for bus master)
0x00
Unimplemented Cache Line Size
0x00
Memory Base Address Register (BAR)
0x00
Claims a 2K address space for the memory mapped UARTs
0xX000
Unimplemented Base Address Register (returns zeros)
0x00000000
Unimplemented Base Address Register (returns zeros)
0x00000000
Unimplemented Base Address Register (returns zeros)
0x00000000
Unimplemented Base Address Register (returns zeros)
0x00000000
Unimplemented Base Address Register (returns zeros)
0x00000000
Reserved
0x00000000
8