XR17C154 Datasheet, PDF (23/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

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REV. 1.3.0
WRITE TX FIFO
Write n+0 to n+3
Write n+4 to n+7
Etc.
BYTE 3
FIFO Data n+3
FIFO Data n+7
BYTE 2
FIFO Data n+2
FIFO Data n+6
XR17C154
5V PCI BUS QUAD UART
BYTE 1
FIFO Data n+1
FIFO Data n+5
BYTE 0
FIFO Data n+0
FIFO Data n+4
Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0300, 0x0500 and 0x0700
Transmit Data Byte n+3
Transmit Data Byte n+2
Transmit Data Byte n+1
Transmit Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 3 is shown in Table 8 below. The THR and RHR
for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit
data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR
register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so
each bus operation can only write or read in bytes.
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible)
CH0 0x000 W rite THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH0 0x000 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x200 W rite THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x200 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH2 0x400 W rite THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH2 0x400 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH3 0x600 W rite THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH3 0x600 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
784THRRHR1
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