XR17C154 Datasheet, PDF (60/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

XR17C154
5V PCI BUS QUAD UART
REV. P1.3.0
TABLE OF CONTENTS
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PRELIMINARY
GENERAL DESCRIPTION ............................................................................................... 1
APPLICATIONS ........................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
Figure 1. Block Diagram ....................................................................................................................... 1
Figure 2. Pin Out of the Device ............................................................................................................ 2
ORDERING INFORMATION ............................................................................................................................ 2
PIN DESCRIPTIONS ....................................................................................................... 3
FUNCTIONAL DESCRIPTION ......................................................................................... 6
PCI Local Bus Interface ...................................................................................................................................... 6
1.0 XR17C154 Registers .............................................................................................................................. 7
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ....................................................................................... 7
Figure 3. The XR17C154 Register Sets ................................................................................................ 7
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ................................................................. 8
1.2 DEVICE CONFIGURATION REGISTER SET ........................................................................................................................ 9
TABLE 2: XR17C154 DEVICE CONFIGURATION REGISTERS ...................................................................... 10
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ............................................ 11
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT ....................................... 11
1.2.1 The Interrupt Status Register ................................................................................................. 12
Figure 4. The Global Interrupt Register, INT0, INT1, INT2 and INT3 ............................................... 13
TABLE 5: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING ............................................................. 13
TABLE 6: UART CHANNEL [3:0] INTERRUPT CLEARING ........................................................................... 13
1.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default
0xXX-XX-00-00) .............................................................................................................................. 14
Figure 5. Timer/Counter circuit. ......................................................................................................... 14
TABLE 7: TIMER CONTROL REGISTERS ............................................................................................... 14
1.2.3 8XMODE [7:0] (default 0x00) ................................................................................................. 15
1.2.4 REGA [15:8] Reserved ........................................................................................................... 15
1.2.5 RESET [23:16] (default 0x00) ................................................................................................ 15
1.2.6 SLEEP [31:24]..................................................................................................(default 0x00) 16
1.2.7 Device Identification and Revision ......................................................................................... 16
1.2.9 Multi-Purpose Inputs and Outputs .......................................................................................... 17
1.2.10 MPIO REGISTER ................................................................................................................. 17
1.2.8 REGB Register ....................................................................................................................... 17
Figure 6. Multipurpose input/output internal circuit ........................................................................ 18
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 20
Figure 7. Typical oscillator connections ........................................................................................... 20
Figure 8. External Clock Connection for Extended Data Rate ........................................................ 20
3.0 Transmit and Receive Data ................................................................................................................. 21
3.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ........................................................... 21
3.1.1 Normal Rx FIFO Data Unloading at locations 0x100, 0x300, 0x500, 0x700 .......................... 21
3.1.2 Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780 .................. 22
3.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700 ......................................... 22
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-BIT
FORMAT ......................................................................................................................................................................... 23
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE .................... 23
4.0 UART ..................................................................................................................................................... 24
4.1 PROGRAMMABLE BAUD RATE GENERATOR .................................................................................................................. 24
Figure 9. Baud Rate Generator ........................................................................................................... 24
4.2 TRANSMITTER ............................................................................................................................................................. 25
4.2.1 Transmit Holding Register (THR) - Write-Only ....................................................................... 25
4.2.2 Transmitter Operation in non-FIFO mode .............................................................................. 25
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING . 25
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