XR17C154 Datasheet, PDF (31/62 Pages) Exar Corporation – 5V PCI BUS QUAD UART

áç
REV. 1.3.0
XR17C154
5V PCI BUS QUAD UART
4.6 Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 16 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held HIGH (idle or de-asserted state), and the CTS#, DSR#
CD# and RI# inputs are ignored.
FIGURE 16. INTERNAL LOOP BACK
VCC
Transmit Shift
Register
MCR bit-4=1
Receive Shift
Register
VCC
RTS#
CTS#
DTR#
VCC
DSR#
RI#
CD#
OP1#
OP2#
TX [3:0]
RX [3:0]
RTS# [3:0]
CTS# [3:0]
DTR# [3:0]
DSR# [3:0]
RI# [3:0]
CD# [3:0]
4.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING
The 4 sets of UART configuration registers are decoded using address lines A8 to A11 as show below. Ad-
dress lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with
EXAR enhanced feature registers located on the upper 8 addresses.
A11 A10 A9
0
0
0
0
0
1
0
1
0
0
1
1
A8 ^{UART CHANNEL}
SELECTION
0
0
0
1
0
2
0
3
31