XRT73LC04A_08 Datasheet, PDF (61/64 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73LC04A
REV. 1.0.2
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
NOTE: Each of these bits is clocked into the SDI input on
the rising edge of SClk.
Bit 1 - R/W (Read/Write) Bit
This bit is clocked into the SDI input, on the first rising
edge of SClk after CS has been asserted. This bit in-
dicates whether the current operation is a Read or
Write operation. A "1" in this bit specifies a Read op-
eration, a "0" in this bit specifies a Write operation.
Bits 2 through 6: The five (5) bit Address Values
(labeled A0, A1, A2 , A3 and A4)
The next five rising edges of the SClk signal clocks in
the 5-bit address value for this particular Read or
Write operation. The address selects the Command
Register in the XRT73LC04A that the user is either
reading data from or writing data to. The address bits
must be supplied to the SDI input pin in ascending or-
der with the LSB (least significant bit) first.
Bit 7:
A5 must be set to "0", as shown in Figure 37.
Bit 8 - A6
The value of A6 is a don't care.
Once these first 8 bits have been written into the Mi-
croprocessor Serial Interface, the subsequent action
depends upon whether the current operation is a
Read or Write operation.
Read Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Read operation proceeds through
an idle period lasting two SClk periods. On the falling
edge of SClk Cycle #8 (see Figure 37) the serial data
output signal (SDO) becomes active. At this point,
reading the data contents of the addressed Com-
mand Register at Address [A4, A3, A2, A1, A0] via
the SDO output pin can begin. The Microprocessor
Serial Interface outputs this five bit data word (D0
through D4) in ascending order with the LSB first on
the falling edges of the SClk pin. Consequently, the
data on the SDO output pin is sufficiently stable for
reading by the Microprocessor on the very next rising
edge of the SClk pin.
Write Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Write operation proceeds through
an idle period lasting two SClk periods. Prior to the
rising edge of SClk Cycle # 9 (see Figure 37). Apply
the desired eight bit data word to the SDI input pin via
the Microprocessor Serial Interface. The Micropro-
cessor Serial Interface latches the value on the SDI
input pin on the rising edge of SClk. Apply this word
(D0 through D7) serially, in ascending order with the
LSB first.
Simplified Interface Option
The design of the circuitry connecting to the Micro-
processor Serial Interface can be simplified by tying
both the SDO and SDI pins together and reading data
from and/or writing data to this combined signal. This
simplification is possible because only one of these
signals are active at any given time. The inactive sig-
nal is tri-stated.
NOTES:
1. A5 is always "0"
2. R/W = "1" for Read Operations
3. R/W = "0" for Write Operations
4. Shaded box denotes a “don't care” value
FIGURE 37. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
R/W A0 A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7
High Z
High Z
D0 D1 D2 D3 D4 0 0 0
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