XRT73LC04A_08 Datasheet, PDF (28/64 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73LC04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM DESCRIPTION
A functional block diagram of the XRT73LC04A E3/
DS3/STS-1 Transceiver IC is presented in Figure 13.
The XRT73LC04A contains four separate channels
with three distinct sections:
• The Transmit Section - Channels 0, 1, 2, and 3
• The Receive Section - Channels 0, 1, 2, and 3
• The Microprocessor Serial Interface Section
THE TRANSMIT SECTION - CHANNELS 0, 1, 2,
AND 3
The Transmit Section, within each Channel, accepts
TTL/CMOS level signals from the Terminal Equip-
ment in either a Single-Rail or Dual-Rail format. The
Transmit Section then takes this data and does the
following:
• Encode this data into the B3ZS format if the DS3 or
SONET STS-1 Modes has been selected or into
the HDB3 format if the E3 Mode has been selected.
• Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
• Drive these pulses onto the line via the TTIP_(n)
and TRing_(n) output pins across a 1:1 Trans-
former.
NOTE: The Transmit Section drives a "1" (or a Mark) onto
the line by driving either a positive or negative polarity pulse
across the 1:1 Transformer within a given bit period. The
Transmit Section drives a "0" (or a Space) onto the line by
driving no pulse onto the line.
THE RECEIVE SECTION - CHANNELS 0, 1, 2 AND
3
The Receive Section, within each Channel, receives
a bipolar signal from the line via the RTIP and RRing
signals through a 1:1 Transformer or 0.01µF Capaci-
tor.
The recovered clock and data outputs to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS_(n), RNEG_(n) and RxClk_(n)
output pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT73LC04A can be configured to operate in ei-
ther the Hardware Mode or the HOST Mode.
The XRT73LC04A contains four identical channels.
The Microprocessor Interface Inputs are common to
all channels. The descriptions that follow refer to
Channel(n) where (n) represents channel 0, 1, 2 or 3.
a. Operating in the Hardware Mode
When the XRT73LC04A is operating in the Hardware
Mode, then the following is true:
1. The Microprocessor Serial Interface block is dis-
abled.
2. The XRT73LC04A is configured via input pin set-
tings.
The XRT73LC04A can be configured to operate in
the Hardware Mode by tying the HOST/(HW) input
pin to GND.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as de-
fined inTable 1.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL
INTERFACE PINS WHEN THE XRT73LC04A IS
OPERATING IN THE HARDWARE MODE
PIN #
PIN NAME
69
CS/(SR/DR)
70
SClk/(RxOFF)
71
SDI/(E3_1)
72
SDO/(E3_0)
110 REGR/(RxClkINV)
FUNCTION, WHILE IN
HARDWARE MODE
(SR/DR)
RxOFF
E3_1
E3_0
RxClkINV
When the XRT73LC04A is operating in the Hardware
Mode, all of the remaining input pins become active.
b. Operating in the HOST Mode
The XRT73LC04A can be configured to operate in
the HOST Mode by tying the HOST/(HW) input pin to
VDD.
When the XRT73LC04A is operating in the HOST
Mode, then the following is true.
1. The Microprocessor Serial Interface block is
enabled. Writing the appropriate data into the
on-chip Command Registers makes many config-
uration selections.
2. All of the following input pins are disabled and
should be connected to ground:
• Pins 43, 44, 137 & 138 - TxLEV_(n)
• Pins 45, 46, 135 & 136 TAOS_(n)
• Pin 82, 90, 91 & 99 - REQEN_(n)
• Pin 77, 85, 96 & 104 - RLB_(n)
• Pin 76, 84, 97 & 105 - LLB_(n)
• Pin 107 & 108 - E3_(n)
• Pin 73, 83, 98 &106 - STS-1/DS3_(n)
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