XRT73LC04A_08 Datasheet, PDF (43/64 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73LC04A
REV. 1.0.2
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Decoder detects this particular pattern, then it substi-
tutes these bits with a “0000" pattern.
Figure 25 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns, in the in-
coming Dual-Rail Data Stream.
FIGURE 25. AN EXAMPLE OF HDB3 DECODING
Line Signal
00 0 V
RCLK
B 00 V
RPOS
RNEG
Data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) "0's" in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High".
3.4.3 Configuring the HDB3/B3ZS Decoder
The XRT73LC04A can enable or disable the HDB3/
B3ZS Decoder blocks by either of the following
means.
a. Operating in the HOST Mode
Enable the HDB3/B3ZS Decoder block of Channel(n)
by writing a "0" into the (SR/DR)_(n) bit-field within
Command Register CR3-(n), as illustrated below.
COMMAND REGISTER CR3-(n)
D4
D3
D2
D1
D0
(SR/DR)_(n)
LOSMUT_(n)
RxOFF
RxClk_(n)INV
Reserved
0
X
X
X
X
b. Operating in the Hardware Mode
To globally enable all HDB3/B3ZS Decoder blocks,
pull the CS/(SR/DR)_(n) input pin "Low". To globally
disable all HDB3/B3ZS Decoder blocks and configure
the device to transmit and receive in an AMI format by
pulling the CS/(SR/DR)_(n) input pin "High".
3.5 LOS DECLARATION/CLEARANCE
Each channel contains circuitry that monitors the fol-
lowing two parameters associated with the incoming
line signals.
1. The amplitude of the incoming line signal via the
RTIP and RRing inputs.
2. The number of pulses detected in the incoming
line signal within a certain amount of time.
If a given channel determines that the incoming line
signal is missing either due to insufficient amplitude
or a lack of pulses in the incoming line signal, then it
declares a Loss of Signal (LOS) condition. The chan-
nel declares the LOS condition by toggling its respec-
tive RLOS_(n) output pin “High" and by setting its cor-
responding RLOS_(n) bit field within Command Reg-
ister 0 (or Command Register 8) to "1".
Conversely, if the channel determines that the incom-
ing line signal has been restored (e.g., there is suffi-
cient amplitude and pulses in the incoming line sig-
nal), then it clears the LOS condition by toggling its
respective RLOS_(n) output pin “Low" and setting its
corresponding RLOS_(n) bit-field to "0".
In general, the LOS Declaration/Clearance scheme
that is employed in the XRT73LC04A is based upon
ITU-T Recommendation G.775 for both E3 and DS3
applications.
3.5.1 The LOS Declaration/Clearance Criteria
for E3 Applications
39