XRT73LC04A_08 Datasheet, PDF (5/64 Pages) Exar Corporation – 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

XRT73LC04A
REV. 1.0.2
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
1.0 SELECTING THE DATA RATE ............................................................................................................... 25
1.1 CONFIGURING CHANNEL(N) ............................................................................................................ 25
Table 2:Hexadecimal Addresses and Bit Formats of XRT73LC04A Command Registers ............................ 26
Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode)
27
COMMAND REGISTER, CR4-(N) ........................................................................................................... 27
Table 4:Selecting the Data Rate for Channel(n) via the STS-1/DS3_(n) and the E3_(n) bit-fields within the Ap-
propriate Command Register (HOST Mode) ..................................................................................... 27
2.0 THE TRANSMIT SECTION ...................................................................................................................... 28
2.1 THE TRANSMIT LOGIC BLOCK ......................................................................................................... 28
Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 28
Figure 14. The typical interface for the Transmission of Data in a Dual-Rail Format from the Transmitting Ter-
minal Equipment to the Transmit Section of a channel .................................................................... 28
Figure 15.The XRT73LC04A Samples the data on the TPData and TNData input pins ................................ 28
Accepting Single-Rail Data from the Terminal Equipment ................................................................ 29
COMMAND REGISTER CR3-(N) ............................................................................................................ 29
Figure 16.The Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is Accepting Sin-
gle-Rail Data from the Terminal Equipment ..................................................................................... 29
2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY ................................................................. 29
2.3 THE HDB3/B3ZS ENCODER BLOCK ............................................................................................... 29
B3ZS Encoding .................................................................................................................................. 29
Figure 17.An Example of B3ZS Encoding ...................................................................................................... 30
HDB3 Encoding ................................................................................................................................. 30
Figure 18.An Example of HDB3 Encoding ..................................................................................................... 30
Disabling the HDB3/B3ZS Encoder ................................................................................................... 30
COMMAND REGISTER CR3-(N) ............................................................................................................ 31
2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY .................................................................................... 31
Figure 19.The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications .................... 31
Figure 20.The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... 32
Enabling the Transmit Line Build-Out Circuit ..................................................................................... 32
COMMAND REGISTER, CR1-(N) ........................................................................................................... 32
Disabling the Transmit Line Build-Out Circuit .................................................................................... 32
COMMAND REGISTER, CR1-(N) ........................................................................................................... 33
Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... 33
The Transmit Line Build-Out Circuit and E3 Applications .................................................................. 33
2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73LC04A TO THE LINE ................................... 33
Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73LC04A to the Line . 33
TRANSFORMER RECOMMENDATIONS .................................................................................................... 34
3.0 THE RECEIVE SECTION ......................................................................................................................... 35
3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73LC04A TO THE LINE ..................................... 35
Figure 22.Recommended Schematic for Interfacing the Receive Section of the XRT73LC04A to the Line (Trans-
former-Coupling) .............................................................................................................................. 35
3.2 THE RECEIVE EQUALIZER BLOCK ................................................................................................... 36
Figure 23.The Typical Application for the System Installer ............................................................................ 36
Guidelines for Setting the Receive Equalizer ................................................................................... 36
II