XRT75L06 Datasheet, PDF (58/63 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

XRT75L06
REV. 1.0.3
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0
JA0_n This bit along with JA1_n bit configures the Jitter
0
Attenuator as shown in the table below.
JA0_n
JA1_n
Mode
0
0
16 bit FIFO
0x07 (Ch 0) R/W Jitter
0
1
32 bit FIFO
0x17 (Ch 1)
0x27 (Ch 2)
0x37 (ch 3)
0x47 (ch 4)
Attenuator
1
0
Disable Jitter
Attenuator
1
1
Disable Jitter
Attenuator
0x57 (ch 5)
D1 JATx/Rx_n Setting this bit selects the Jitter Attenuator in the
0
Transmit Path. A “0” selects in the Receive Path.
D2
JA1_n This bit along with the JA0_n configures the Jitter
0
Attenuator as shown in the table.
D3 PNTRST_n Setting this bit resets the FIFO pointers to their initial
0
state and flushes the FIFO. All existing FIFO data is
lost.
D4 DFLCK_n Set this bit to “1” to disable fast locking of the PLL.
0
This helps to reduce the time for the PLL to lock to
incoming frequency when the Jitter Attenuator
switches to narrow band.
D7-D5
Reserved
55