XRT75L06 Datasheet, PDF (55/63 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06
REV. 1.0.3
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMO_n This bit is set when no transitions on the TTIP/
0
TRING have been detected for 128 ± 32 TxCLK
periods.It will be cleared when pulses resume.
D1 RLOS_n This bit is set every time the receiver declares an
0
LOS condition.It will be cleared when the signal is
recognized again.
D2 RLOL_n This bit is set when the detected clock is greater
0
0x03 (ch 0)
0x13 (ch 1)
0x23 (ch 2)
0x33 (ch 3)
Read Alarm Sta-
Only tus
than 0.5% oof frequency from the reference clock.By
definition, the two frequencies are “not in lock” with
each other. It will be cleared when they are “in lock”
again..
0x43 (ch 4)
0x53 (ch 5)
D3
FL_n This bit is set when the FIFO reaches its limit.The
0
limit is defined to be within two bits of either under-
flow or overflow.
D4 ALOS_n This bit is set when the receiver declares that the
0
Analog signal has degraded to the point that the sig-
nal has been lost.
D5 DLOS_n This bit is set when no input signals have been
0
received for 10 to 255 bit times in E3 or 100 to 250
bit times in DS3 or STS-1 modes.This is a complete
lack of incoming pulses rather than signal attenua-
tion (ALOS). It should be noted that this time period
is built into the Analog detector for E3 mode. Even
though DS3/STS-1 mode does not require analog
detection level, but it is provided and could help to
determine the “quality of the line” for DS/STS-1
applications.
D6 PRBSLS_n This bit is set when the PRBS detector has been
0
enabled and it is not in sync with the incoming data
pattern. Once the sync is achieved, it will be cleared.
D7
Reserved
52