XRT75L06 Datasheet, PDF (49/63 Pages) Exar Corporation – SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75L06
REV. 1.0.3
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
PCLK
Addr[7:0]
CS
D[7:0]
RD
WR
RDY
READ OPERATION
t₀
Valid Address
WRITE OPERATION
t₀
Valid Address
Valid Data for Readback
t₁
t₂
Data Available to Write Into the LIU
t₃
t₄
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL
t₀
t₁
t₂
NA
t₃
t₄
NA
PARAMETER
Valid Address to CS Falling Edge
CS Falling Edge to RD Assert
RD Assert to RDY Assert
RD Pulse Width (t₂)
CS Falling Edge to WR Assert
WR Assert to RDY Assert
WR Pulse Width (t₄)
PCLK Period
PCLK Duty Cycle
PCLK "High/Low" time
MIN
0
MAX
-
UNITS
ns
0
-
ns
-
35
ns, see note 1
40
-
ns
0
-
ns
-
35
ns, see note 1
40
-
ns
15
ns
NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
time, use the following formula: (PCLK_period * 2) + 5ns
46