XR16M564 Datasheet, PDF (55/55 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.0
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 29
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 29
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 30
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31
TABLE 13: PARITY SELECTION ........................................................................................................................................................ 32
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 32
TABLE 14: INT OUTPUT MODES ..................................................................................................................................................... 33
4.8 LINE STATUS REGISTER (LSR) - READ/WRITE ............................................................................................ 34
4.9 MODEM STATUS REGISTER (MSR) - READ/WRITE...................................................................................... 35
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 35
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE................................................. 36
TABLE 15: SAMPLING RATE SELECT ............................................................................................................................................... 36
4.12 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 36
TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37
4.13 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE................... 38
TABLE 17: UART RESET CONDITIONS FOR CHANNELS A-D .................................................................................................. 39
ABSOLUTE MAXIMUM RATINGS.................................................................................. 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40
ELECTRICAL CHARACTERISTICS ............................................................................... 40
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 41
TA = -40O TO +85OC, VCC IS 1.62 TO 3.63V, 70 PF LOAD WHERE APPLICABLE ........................................... 41
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 42
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 43
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D.................................................................................... 43
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 44
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 45
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 45
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 46
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 47
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 47
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 48
PACKAGE DIMENSIONS ................................................................................................................................ 49
REVISION HISTORY...................................................................................................................................... 53
2