XR16M564 Datasheet, PDF (39/55 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

REV. 1.0.0
XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
TABLE 17: UART RESET CONDITIONS FOR CHANNELS A-D
REGISTERS
RESET STATE
DLM, DLL
DLM = 0x00 and DLL = 0x01. Only resets to these val-
ues during a power up. They do not reset when the
Reset Pin is asserted.
DLD
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
HIGH
RTS#
HIGH
DTR#
HIGH
RXRDY#
HIGH
TXRDY#
LOW
INT
(16 Mode)
XR16M564 = Three-State Condition (INTSEL = LOW)
XR16M564 = LOW (INTSEL = HIGH)
XR16M564D = LOW
IRQ#
(68 Mode)
Three-State Condition (INTSEL = LOW)
39