XR16M564 Datasheet, PDF (36/55 Pages) Exar Corporation – 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO

XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.0
4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate
divisor. DLD must be enabled via EFR bit-4 before it can be accessed. See Table 15 below and See ”Section
2.8, Programmable Baud Rate Generator with Fractional Divisor” on page 13.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 15 below.
TABLE 15: SAMPLING RATE SELECT
DLD[5]
DLD[4]
SAMPLING RATE
0
0
16X
0
1
8X
1
X
4X
DLD[7:6]: Reserved
4.12 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 16). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
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