XR16M752_09 Datasheet, PDF (53/54 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. XR16M752 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT - TQFP AND QFN PACKAGES ....................................................................................................... 2
FIGURE 3. PIN OUT ASSIGNMENT - STBGA PACKAGE ...................................................................................................................... 3
ORDERING INFORMATION ............................................................................................................................... 3
PIN DESCRIPTIONS ........................................................................................................ 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10
2.1 CPU INTERFACE .............................................................................................................................................. 10
FIGURE 4. XR16M752/XR68M752 DATA BUS INTERCONNECTIONS................................................................................................ 10
2.2 DEVICE RESET ................................................................................................................................................. 11
2.3 CHANNEL A AND B SELECTION .................................................................................................................... 11
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE .......................................................................................................................... 11
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE .......................................................................................................................... 11
2.4 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................. 11
2.5 DMA MODE ....................................................................................................................................................... 12
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ........................................................................................... 12
2.6 INTA AND INTB OUTPUTS............................................................................................................................... 12
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 12
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 12
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 13
FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 13
2.8 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 13
FIGURE 6. BAUD RATE GENERATOR ............................................................................................................................................... 14
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 15
2.9 TRANSMITTER.................................................................................................................................................. 15
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 16
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 16
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 16
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 16
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 16
2.10 RECEIVER ....................................................................................................................................................... 17
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 17
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 17
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 18
2.11 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 18
2.12 AUTO RTS HALT AND RESUME .................................................................................................................. 18
2.13 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 18
2.14 AUTO CTS FLOW CONTROL........................................................................................................................ 19
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 19
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 20
2.16 SPECIAL CHARACTER DETECT.................................................................................................................. 20
2.17 INFRARED MODE ........................................................................................................................................... 20
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 21
2.18 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE FEATURE ........................................... 22
2.19 SLEEP MODE WITH AUTO WAKE-UP .......................................................................................................... 22
2.19.1 POWERSAVE FEATURE (49-PIN STBGA PACAKGE ONLY) ................................................................................. 22
2.20 INTERNAL LOOPBACK................................................................................................................................. 23
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 23
3.0 UART INTERNAL REGISTERS............................................................................................................. 24
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 24
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 25
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 26
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 26
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 26
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