XR16M752_09 Datasheet, PDF (14/54 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a
multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value can be calculated
with the following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
The closest divisor that is obtainable in the M752 can be calculated using the following formula:
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 6. BAUD RATE GENERATOR
To Other
Channel
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL, DLM and DLD
Registers
MCR Bit-7=0
(default)
Fractional Baud
Rate Generator
Logic
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
MCR Bit-7=1
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