XR16M752_09 Datasheet, PDF (4/54 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
REV. 1.1.1
Pin Description
NAME
32-QFN
PIN #
48-TQFP 49-STBGA
TYPE
PIN #
PIN #
DESCRIPTION
DATA BUS INTERFACE
A2
18
26
A1
19
27
A0
20
28
D7
2
3
D6
1
2
D5
32
1
D4
31
48
D3
30
47
D2
29
46
D1
28
45
D0
27
44
IOR#
14
19
(NC)
IOW#
12
15
(R/W#)
CSA#
7
10
(CS#)
CSB#
8
11
(A3)
G7
I _{Address data lines [2:0]. These 3 address lines select}
E7
one of the internal registers in UART channel A/B during
E6
a data bus transaction.
C2
I/O _{Data bus lines [7:0] (bidirectional).}
C1
B1
B2
A2
B4
B3
A3
G4
I _{When 16/68# pin is HIGH, the Intel bus interface is}
selected and this input becomes read strobe (active low).
The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed
by the address lines [A2:A0], puts the data byte on the
data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input is not used.
F2
I _{When 16/68# pin is HIGH, it selects Intel bus interface}
and this input becomes write strobe (active low). The fall-
ing edge instigates the internal write cycle and the rising
edge transfers the data byte on the data bus to an inter-
nal register pointed by the address lines.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input becomes read (HIGH) and write
(LOW) signal.
E2
I _{When 16/68# pin is HIGH, this input is chip select A}
(active low) to enable channel A in the device.
When 16/68# pin is LOW, this input becomes the chip
select (active low) for the Motorola bus interface.
E1
I _{When 16/68# pin is HIGH, this input is chip select B}
(active low) to enable channel B in the device.
When 16/68# pin is LOW, this input becomes address
line A3 which is used for channel selection in the Motor-
ola bus interface. Input logic 0 selects channel A and
logic 1 selects channel B.
4