XR16M752_09 Datasheet, PDF (25/54 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

REV. 1.1.1
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
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TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS ^{REG READ/}
A2-A0 ^{NAME WRITE}
BIT-7
BIT-6
BIT-5
BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
16C550 Compatible Registers
0 0 0 RHR RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7
Bit-6
Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/ Modem RX Line TX RX Data
CTS Int. RTS Int.
Enable Enable
Xoff Int.
Enable
Sleep
Mode
Enable
Stat. Int. Stat. Int.
Enable Enable
Empty
Int
Enable
Int.
Enable
0 1 0 ISR
RD FIFOs FIFOs
0/
0/
INT
INT
INT
INT
Enabled Enabled
Source Source Source Source
INT
INT
Bit-3 Bit-2 Bit-1 Bit-0
Source Source
Bit-5 Bit-4
010
FCR
WR RXFIFO RXFIFO 0/
0/
DMA TX FIFO RX FIFOs
Trigger
Trigger
Mode
TXFIFO TXFIFO _Enable
Trigger Trigger
Reset
FIFO
Reset
Enable
COMMENT
LCR[7]=0
011
100
101
LCR RD/WR Divisor Set TX Set Par- Even
Enable Break
ity
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
MCR RD/WR
0/
Clock
Pres-
caler
Select
0/
TCR and
TLR
ENable
0/
XonAny
Internal OP2#/
Lopback INT Out-
Enable put
Enable
FIFO
Rdy
Enable
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LSR RD RX FIFO THR & THR
RX
RX
RX
RX RX Data
Global TSR Empty Break Framing Parity Over- Ready
Error Empty
Error Error run
Error
LCR≠0xBF
110
111
110
111
111
MSR RD
CD# RI# Input DSR#
Input
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
See Table 13
SPR RD/WR Bit-7
Bit-6
Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0 See Table 12
TCR RD/WR Resume Resume Resume Resume Halt
Bit-3
Bit-2
Bit-1
Bit-0
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt _{See Table 13}
Bit-0
TLR RD/WR RX Trig
Bit-3
RX Trig
Bit-2
RX Trig
Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig TX Trig
Bit-2 Bit-1
TX Trig
Bit-0
See Table 12
FIFO RD
0
Rdy
0 RX FIFO RX FIFO 0
B Status A Status
0
TX FIFO
B Status
TX FIFO
A Status
See Table 12
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