XR16M752_09 Datasheet, PDF (20/54 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
2.15 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the M752 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the M752 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the M752 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the M752 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to 0x00. Following reset the user can
write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/Xoff
characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the M752 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the M752 automatically
sends the Xoff-1,2 via the serial TX output to the remote modem when the RX FIFO reaches the Halt Level
(TCR[3:0]). To clear this condition, the M752 will transmit the programmed Xon-1,2 characters as soon as RX
FIFO falls down to the Resume Level.
2.16 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The M752 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison.
2.17 Infrared Mode
The M752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder can be enabled by setting DLD register bit-7 to a ‘1’. When the infrared
feature is enabled, the transmit data output, TX, idles LOW. Likewise, the RX input also idles LOW, see
Figure 12. In the 49-pin STBGA package, this feature can be enabled upon power-up by connecting the
ENIR# pin of the STBGA package to GND. If the IR mode is enabled via the ENIR# pin, it can be disabled
after power-up via DLD bit-7.
The wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each
time it senses a light pulse, it returns a logic 1 to the data bit stream.
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