XR16M752_09 Datasheet, PDF (36/54 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. There are also
two other registers (TLR and FIFO Rdy) that share the same address location as the Scratch Pad Register.
See Table 12.
4.11 Transmission Control Register (TCR) - Read/Write (requires EFR bit-4 = 1)
This register replaces MSR and is accessible only when MCR[6] = 1. This 8-bit register is used to store the RX
FIFO threshold levels to halt/resume transmission during hardware or software flow control.
TCR[3:0]: RX FIFO Halt Level
A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX
FIFO is greater than or equal to this value, the RTS# output will be de-asserted if Auto RTS flow control is used
or the XOFF character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that
this value is greater than the RX Trigger Level.
TCR[7:4]: RX FIFO Resume Level
A value of 0-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the Resume Level. When the
RX FIFO is less than or equal to this value, the RTS# output will be re-asserted if Auto RTS flow control is used
or the XON character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this
value is less than the RX Trigger Level.
4.12 Trigger Level Register (TLR) - Read/Write (requires EFR bit-4 = 1)
This register replaces SPR and is accessible under the conditions listed in Table 12. This 8-bit register is used
to store the RX and TX FIFO trigger levels used for interrupts.
TLR[3:0]: TX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the TX FIFO Trigger Level.
When the number of available spaces in the TX FIFO is greater than or equal to this value, a Transmit Ready
interrupt is generated. For any non-zero value, TCR[3:0] will be used as the TX FIFO Trigger Level. If
TCR[3:0] = 0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4]. See Table 10.
TLR[7:4]: RX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the RX FIFO Trigger Level.
When the number of characters received in the RX FIFO is greater than or equal to this value, a Receive Data
Ready interrupt is generated (a Receive Data Timeout interrupt is independent of the RX FIFO Trigger Level
and can be generated any time there is at least 1 byte in the RX FIFO and the RX input has been idle for the
timeout period described in “Section 2.10, Receiver” on page 17). For any non-zero value, TCR[7:4] will be
used as the RX FIFO Trigger Level. If TCR[7:4] = 0x0, then the RX FIFO Trigger Level is the value selected by
FCR[7:6]. See Table 10.
4.13 Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. SEE ”PROGRAMMABLE BAUD RATE GENERATOR
WITH FRACTIONAL DIVISOR” ON PAGE 13.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below.
DLD[5]
0
TABLE 14: SAMPLING RATE SELECT
DLD[4]
0
SAMPLING RATE
16X
36