XR16V2752_07 Datasheet, PDF (51/51 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

XR16V2752
REV. 1.0.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 25
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 26
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 28
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 30
4.8 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 32
4.9 SCRATCH PAD REGISTER (SPR) - READ/WRITE ......................................................................................... 33
4.10 ENHANCED MODE SELECT REGISTER (EMSR) ......................................................................................... 33
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 33
TABLE 13: AUTO RTS HYSTERESIS ................................................................................................................................................ 34
4.11 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ............................................................................................ 34
4.12 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 34
4.13 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ........................................................................ 34
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY................................................................................. 35
4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY .................................................................................... 35
4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 35
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .......................................................................... 35
TABLE 14: TRIGGER TABLE SELECT ............................................................................................................................................... 36
4.19 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 36
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 37
4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 38
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39
ABSOLUTE MAXIMUM RATINGS ................................................................................. 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40
ELECTRICAL CHARACTERISTICS............................................................................... 40
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 40
TA=-40o to +85oC, Vcc is 2.25V to 3.6V ............................................................................................................... 40
AC ELECTRICAL CHARACTERISTICS............................................................................................................. 41
Unless otherwise noted: TA=-40o to +85oC, Vcc=2.25 - 3.63V, 70 pF load where applicable................................ 41
FIGURE 13. CLOCK TIMING............................................................................................................................................................. 42
FIGURE 14. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 42
FIGURE 16. DATA BUS WRITE TIMING ............................................................................................................................................ 43
FIGURE 15. DATA BUS READ TIMING .............................................................................................................................................. 43
FIGURE 17. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 44
FIGURE 18. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 44
FIGURE 19. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 45
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 45
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 46
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 46
PACKAGE DIMENSIONS (44 PIN PLCC) ...................................................................... 47
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm).............................................. 48
REVISION HISTORY ..................................................................................................................................... 49
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